EE272B - Design Projects in VLSI Systems II

Bandgap Voltage Reference

John Kustin

Code: Design, Caravel User Project Analog

Documentation: Proposal, Design Review, Final Presentation, Report, Silicon Results

A bandgap reference is a common way to generate a stable voltage with low sensitivities to temperature and supply voltage changes. This project is a CMOS bandgap reference circuit based on the Banba architecture and implemented in SkyWater 130 nm technology. The circuit consists of a self-biased CMOS op-amp, parasitic PNP transistors, resistors, and metal-in-metal (MiM) capacitors. It is designed for a reference voltage of 970.3 mV with an ideal temperature coefficient of 3.6 ppm/°C from 0-70°C. The circuit is open-source and verified to be fully functional in silicon.

OpenPMIC: A Current Mode Buck Converter

Weston Braun, Aparna Tumkur

Code: Design, Caravel User Project Analog, OpenPMIC PCB

Documentation: Proposal, Design Review, Final Presentation, Silicon Results

OpenPMIC is a current mode buck converter in SkyWater 130 nm technology designed using a fully open source flow. It also provides a library of power MOS devices for use in future open source designs. This DC-DC converter is designed to convert the 3.3 V I/O voltage to the 1.8 V level required for digital logic and is intended for integration into other projects. The prototype chip achieves a measured power efficiency of 85% at the maximum output power of 720 mW and a peak efficiency of 91% at an output power of 270 mW. This work is the first open-source and silicon-proven PMIC.

OpenSourcePHY: A High Speed Serial Link

Can Wang, Estelle He

Code: Design, Caravel User Project Analog

Documentation: Proposal, Design Review, Final Presentation, Silicon Bringup Progress

OpenSourcePHY is an open-source fully synthesizable high speed serial link physical layer (PHY) in SkyWater 130 nm technology, which extends the DragonPHY project. This chip focuses on the transmitter portion of the PHY, which consists of a serializer that aggregates multiple inputs at a relatively low data rate into a single high-speed data output, a driver stage that launches the signal into the physical channel and a clocking circuit that uses a multiplying delay-locked loop (MDLL).

A Mixed-Signal Edge Accelerator for Real-Time mmWave Platform Vibration Compensation

Nikhil Poole

Paper: IEEE Access, Hot Chips 2023

Code: Design, Caravel User Project Analog

Documentation: Proposal, Design Review, Final Presentation, Silicon Results

This analog/mixed-signal chip is an edge processing unit for real-time vibratory motion compensation in a mmWave radar platform, employing on-chip inertial sensor fusion to deconvolve the effect of parasitic platform micromotions. With its fully analog IMU processing pipeline and digital deconvolution kernel estimator core, the chip generates a complex inverse filter to denoise the incoming radar data, thereby demonstrating a real-time solution for high-fidelity edge-based radar processing.

Wakey-Wakey: A Low-Power, Reconfigurable Wake Word Accelerator

Matthew Pauly, Eldrick Millares

Code: Design, Caravel User Project

Documentation: Proposal, Design Review, Final Presentation, Report, Silicon Bringup Progress

Wakey-Wakey is an acoustic featurization and deep neural network (DNN) accelerator which detects a user-configured wake word in human speech. It interfaces directly with an external microphone and can be configured via a Wishbone bus. Wakey-Wakey's custom DNN architecture and featurization pipeline were co-optimized with its RTL design to minimize area, power, complexity, and latency.

CryptoChip: A RISC-V Processor with Crypto Accelerator

Kylee Krzanich, Sam Xu

Code: Design, Caravel User Project

Documentation: Proposal, Design Review, Final Presentation, Report

In a world where security has become more and more important, this project focuses on designing a crypto-accelerator for a modern RISC-V processor. It achieves 17-66x increase in performance for all cryptographic transactions including but not limited to random number generation and encryption. The accelerator is designed as a tighly-coupled co-processor to a general purpose, RISC-V processor generated using Chipyard.

A RISC-V OoO Processor with Victim Caches

George Klimiashvili, Ismael Garcia

Code: Design, Caravel User Project

Documentation: Proposal, Design Review, Final Presentation

This project designs an out of order (OoO) RISC-V processor based on the BOOM core using the Chipyard framework. The project performs design space exploration of BOOM core parameters to create a design that fits within the caravel user project design constraints. It also explores the benefit of adding a victim cache, which is a small fully-associative cache that holds recently evicted data, to the core.

Toy-CGRA: A Coarse-Grained Reconfigurable Array for Flexible Acceleration of Machine Learning and Image Processing

Po-Han Chen, Charles Tsao

Paper: ISCAS 2023

Code: Design, Caravel User Project

Documentation: Proposal, Design Review, Final Presentation, Silicon Bringup Progress

Toy-CGRA is a 4x8 coarse-grained reconfigurable array (CGRA) that enables hardware acceleration of machine learning and image processing applications written in Halide. Compared to an FPGA, it provides faster configuration time and lower power consumption. Compared to an ASIC, it has higher flexibility. Toy-CGRA runs at 66 MHz and occupies an area of 3.5 mm x 2.9 mm.