EE372 - Design Projects in VLSI Systems II

Fast ANN Fieldious: An Approximate Nearest-Neighbor (ANN) Field Hardware Accelerator

Chris Calloway, Jake Ke

Code: Design, Caravel User Project

Documentation: Proposal, Design Review, Final Presentation, Report

Fast ANN Fieldious is a hardware accelerator for computing approximate nearest neighbor fields (ANNF). This is an important but computationally expensive calculation needed for computer vision tasks such as optical flow, video compression and image pattern matching. Our accelerator implements a parallelized and pipelined version of the propagation assisted K-D tree algorithm for computing ANNF. The design runs at a clock frequency of 150 MHz, and achieves a throughput of 5.74M vectors/seconds with a power consumption of 204 mW.

OpenPUF: A Bistable Ring Physical Unclonable Function

Luke Sammarone, Xiaolin Wu

Code: Design, Caravel User Project Analog

Documentation: Proposal, Design Review, Final Presentation, Report

Physical unclonable functions (PUFs) contain cryptographic secrets not in the form of digital values stored in memory, but in the physical characteristics of the hardware itself, enabling authentication and secret key generation securely and energy efficiently. This chip features four instances of 32-bit, 64-bit, and 128-bit bistable ring PUFs for characterization of stability, uniqueness, and settling time. The PUF super block occuies an area of 1.02 square mm and shows 48% uniqueness in post-layout simulation.

Kairos: A Vector Processor for Error-State Extended Kalman Filter Acceleration

Jeffery Yu, Yuchen Mei

Code: Design, Caravel User Project

Documentation: Proposal, Design Review, Final Presentation, Report

Kairos is a SIMD single precision floating point vector processor, with instructions conforming to the RISC-V ISA. It implements operations such as vector fused multipy-add, matrix inversion, and matrix multiply-add, to efficiently accelerate error-state extended Kalman filter (ES-EKF) for trajectory estimation.

12-bit 10-KSPS Incremental Delta-Sigma ADC in Skywater 130 nm

Raymond Yang, Yaqing Xia

Paper: IEEE Design & Test

Code: Design, Caravel User Project Analog

Documentation: Proposal, Design Review, Final Presentation, Report

This project is a 12-bit 10 KSPS incremental delta-sigma analog-to-digital converter (ADC) designed for sensor interface and instrumentation applications. The ADC consists of a second-order incremental modulator and three post-integrators. The total area of the ADC is 0.55 square mm, with 0.53 square mm for analog modulator and 0.02 square mm for digital filter.

Grapevine: An Asynchronous Numerical Classifier Using Sparse Grids

Leo Liu, Priyanka Dilip

Code: Design, Caravel User Project

Documentation: Proposal, Design Review, Final Presentation

Grid-based numerical methods sample N-dimensional functions at regular intervals to produce an N-dimensional set of discrete “grid points”. By breaking up grid points into hierarchical subgrids and eliminating subgrids above a certain hierarchy, one can obtain a sparsified grid space that reduces computational complexity. Grapevine is a hardware accelerator for solving classification problems using the sparse grid approach. It supports up to 6 dimensions and 256 grid points. Each grid point is implemented using a single processing element (PE). An asynchronous network-on-a-chip overlays the PEs to provide low-latency multicast routing.

Automated Analog Layout of Bandgap Reference Circuit

Yueting Li, Xingyu Ni

Code: Design, Caravel User Project Analog

Documentation: Proposal, Design Review, Final Presentation, Report

This project ports an automatic analog layout generation tool called aloe to work with SkyWater 130 nm technology. Aloe uses a digital place and route tool together with a genetic algorithm to meet different analog layout specifications. Using this tool, we generated several layouts for a bandgap voltage reference circuit on this chip, and we will compare these with a manually laid out version from the previous offering of this course.

OpenEnclave: A Basic BGV Homomorphic Encryption Accelerator

Ian MacFarlane, JD Kelly

Code: Design, Caravel User Project

Documentation: Proposal, Design Review, Final Presentation, Report

Homomorphic encryption is a promising technique to enable secure computation on sensitive data. It has particualy seen significant interest for use in cloud based machine learning. OpenEnclave is an open-source hardware accelerator for the BGV fully homomorphic encryption scheme in SkyWater 130 nm technology. The design is capable of operating at 50 MHz and is comparable to or outperforms existing FPGA implementations in the literature.